The present invention relates to a transistor matrix device and a method for driving the same, more specifically to a TFT matrix-type liquid crystal display device for use in laptop personal computers and wall televisions, and a method for driving the same.
TFT matrix-type liquid crystal display devices are characterized by thinness and lightness, low electric power consumption, etc., and are expected to have a large market in the future as a display device in place of CRTs. To realize large screens for use in work stations, and TFT panels of high precision, aperture ratios of picture elements are an important subject to obtain higher image qualities.
A liquid crystal panel of the most general normally white mode includes a light shield film which is called a black matrix opposed to the substrate for the purpose of preventing leakage of light between the picture element electrodes, and the drain bus lines and the gate bus lines which deteriorates contrast. In the liquid crystal panel of such structure, it is necessary to take into consideration a margin for aligning the TFT substrate with the opposed substrate, which adds to an area of the light shield film, the black matrix, adversely resulting in low aperture ratios. The aperture ratio is an important parameter on which display quality of the liquid crystal panel depends. For bright display, higher aperture ratios are required.
A liquid crystal capacitance which is a capacitance value of the liquid crystal is also an important parameter on which display quality of the liquid crystal panel depends. Larger liquid crystal capacitances are necessary for higher display qualities.
Thus larger liquid crystal capacitances but nevertheless higher aperture ratios are an important technical subject for liquid crystal panel.
A conventional thin film transistor matrix device is shown in FIGS. 38A and 38B. FIG. 38A shows its pattern layout, and FIG. 38B shows a sectional view along the line A-A'.
With reference to FIG. 38A, the pattern layout of the thin film transistor matrix device will be explained. Picture element electrodes 102 are arranged in a matrix on a transparent insulating substrate 100. Thin film transistors 104 are disposed on the respective picture elements 102. Gate bus lines 106 are provided widthwise as viewed in FIG. 38A and are connected commonly to the gates of the respective thin film transistors 104 are commonly connected to gate bus lines 106. Drain bus lines 108 are provided lengthwise as viewed in FIG. 38A and commonly connected to the drains of the thin film transistors 104.
The structure of each thin film transistor will be detailed with reference to FIG. 38B. A gate electrode 109 is formed on a transparent insulating substrate 100, and a gate insulating film 110 is formed on the gate electrode 109. An amorphous silicon layer 112 to be a channel layer of the thin film transistor is formed on the gate insulating film 110. A channel protection film 114 for protecting the central channel region is provided on the amorphous silicon film 112. n.sup.+ -amorphous silicon layers 116, 118 are formed on both sides of the channel protection film 114 on the amorphous silicon layer 112. A drain electrode 120 is formed on the n.sup.+ -amorphous silicon layer 16, and a source electrode 122 is formed on the n.sup.+ -amorphous silicon layer 118. The thin film transistors 104 are entirely covered with a protection film 124. A picture element electrode 102 is formed on the protection film 124. The picture element electrode 102 and the source electrode 122 are connected through a contact hole 126 formed in the protection film 124.
FIG. 39 shows an equivalent circuit of each thin film matrix device. Each film transistor is provided at each of the intersections between gate bus lines 106 and drain bus lines 108. A liquid crystal capacitance Clc which is a capacitance of the liquid crystal is connected to the source electrode 122 of the thin film transistor 104. A parasitic capacitance Cgs is present between the picture element electrode 102 and the gate bus line 106. A parasitic capacitance Cgs is a total of a capacitance value corresponding to a degree of overlap between the gate electrode 109 and the source electrode 122 of the thin film transistor 104, and a capacitance value generated by the neighborhood between the picture element electrode 102 and the gate bus line 106.
Then, the operation of the thin film transistor matrix device will be explained with reference to FIG. 40.
When a positive pulse is applied to the gate bus line 106, the thin film transistors 104 are turned on, and a required drain voltage VD applied to the drain electrodes 120 is applied to the picture element electrodes 102. By applying a required drain voltage VD at this time, required displays including intensity levels can be available.
However, the presence of a parasitic capacitance Cgs makes it impossible to apply a required drain voltage VD to the picture element electrodes 102. That is, when a required drain voltage VD is applied, and a gate voltage VD is changed from an OFF voltage VGoff to an ON voltage VGon, the thin film transistors 104 are turned on, and the drain voltage VD is applied to the picture element electrodes 102. When the gate voltage VG is changed by .DELTA.VG from the ON voltage VGon to the OFF voltage VGoff, a potential of the picture elements 102 is adversely lowered by .DELTA.V as shown by the following formula, by the capacitive coupling of the parasitic capacitance Cgs. EQU .DELTA.V=Cgs/(Cgs+Clc).multidot..DELTA.VG (1)
Accordingly a direct current noise component .DELTA.V is overlapped on a potential of the picture element electrodes 102 with the result of problems of flickering of liquid crystal displays, poor contrast, lower reliability of decomposition of the liquid crystal and orientation film, etc., printing of liquid crystal displays, etc. As a countermeasure to these problems. a common potential Vc which is a potential of opposed electrodes is lowered by .DELTA.V, so that a required voltage is applied to the liquid crystal.
The liquid crystal capacitance Clc is changed in accordance with the ON/OFF states of the liquid crystal. The liquid crystal capacitance Clc(on) in the state that a voltage is applied to the liquid crystal is larger than the liquid crystal capacitance Clc(off) in the state that no voltage is applied to the liquid crystal. Accordingly a voltage .DELTA.V which is lowered by the capacitive coupling by the parasitic capacitance Cgs varies depending on display states.
Even though a common potential Vc is lowered, the above-described problems, such as printing of liquid crystal displays, occur depending on display states.
To solve these problems, a thin film transistor matrix device including a sub-capacitance disposed parallel with a liquid crystal capacitance has been proposed.
This thin film transistor matrix device is shown in FIGS. 41A to 41C. FIG. 41A shows the pattern layout. FIG. 41B shows the sectional view along the line A-A'. FIG. 41C shows the sectional view along the line B-B'.
With reference to FIG. 41A, the pattern layout of the thin film transistor matrix device will be explained. Picture elements 102 are arranged in a matrix on a transparent insulating substrate 100. A thin film transistor 104 is provided on each picture element electrode 102. Gate bus lines 106 which are commonly connected to the gates of the thin film transistors 104 are provided, and drain bus lines 108 which are commonly connected to the drains of the thin film transistors 104 are provided.
Intermediate electrodes 128 for forming the sub-capacitances Cs are formed below the picture element electrodes 102. Gate bus lines 106 are formed below the intermediate electrodes 128 and in the gaps between the picture elements electrodes 102 along the drain bus lines 108 corresponding to the intermediate electrodes 128.
The structure of the thin film transistor matrix device will be explained with reference to FIGS. 41A and 41B.
The structure of the sub-capacitances Cs is shown in FIG. 41C. That is, a gate bus line 106 is formed on the transparent insulating substrate 100, and an intermediate electrode 128 is formed above the gate bus line 106 through the gate insulating film 110. The intermediate electrode 128 is covered with a protection film 124. A picture element electrode 102 is formed on the protection film 124. The picture electrode 102 and the intermediate electrode 128 are connected through a contact hole 130 formed in the protection film 124.
The equivalent circuit of the thin film transistor matrix device is shown in FIG. 42, and operational waveforms of the thin film transistor matrix device are shown in FIG. 43.
The thin film transistors 104 are disposed at the intersections between the gate bus lines 106 and the drain bus lines 108. Liquid crystal capacitances Clc which are a capacitance of the liquid crystal are connected to the source electrodes 122 of the thin film transistors 104. The sub-capacitances Cs are present between the picture element electrodes 102, and the gate bus lines 106 adjacent to the picture element electrodes 102. The parasitic capacitances Cs have a value corresponding to a degree of overlap between the gate bus lines 106 and the intermediate electrodes 128.
A direct current voltage change .DELTA.V of the picture element electrodes 102 of the thin film transistor matrix device is given by the following formula. EQU .DELTA.V=Cgs/(Cgs+Clc+Cs).multidot.VG (2)
Thus the voltage change .DELTA.V can be made small as shown in FIG. 43 by making the capacitance value Cs of the sub-capacitances larger as much as possible so that (Clc+Cs)&gt;&gt;Cgs, whereby much improved display quality can be available. As shown in FIG. 43, a voltage of the picture element electrodes 102 is changed by writing pulses of the gate bus lines 106 connected to the sub-capacitances Cs, but the change is too short to affect a display quality.
Thus, for the improvement of the display quality it is very effective to provide the sub-capacitances for larger apparent capacitances. To realize this, the sub-capacitances are formed by overlapping parts of the gate bus lines on parts of the picture element electrodes with the insulating film therebetween. That is, a structure called Cs-on-Gate structure has been proposed. The above-described structure of FIGS. 41A to 41C is a Cs-on-Gate structure.
One example of the Cs-on-Gate structure is shown in FIGS. 44A and 44B. FIG. 44A shows the pattern layout, and FIG. 44C shows the sectional view along the line C-C'.
In this thin film transistor matrix device, the pattern for forming the sub-capacitances functions as the black matrix for shielding leakage light, whereby higher aperture ratios can be obtained.
Picture element electrodes 102 are arranged on a transparent insulating substrate 100 in a matrix. A thin film transistor 104 is disposed on each picture element electrode 102. Gate bus lines 106 commonly connected to the gates of the thin film transistors 104, and the drain bus lines 108 commonly connected to the drains of the thin film transistors 104 are provided.
Sub-patterns 132 are provided for covering the gaps between the respective picture element electrodes 102, and those on the left and the right sides of the respective picture element electrodes 102. The sub-patterns 132 overlap the picture element electrodes 102 at peripheral parts thereof, and are continuous to the gate bus lines 106 in an integral pattern.
As shown in FIG. 44B, sub-patterns 132, which are continuous to gate bus lines 106, are formed on the transparent insulating substrate 100, and the gate insulating film 110 is formed on the sub-patterns 132. Drain bus lines 108 are formed on the gate insulating film 110, and a protection film 124 is formed on the drain bus lines 108. Picture element electrodes 102 are formed on the protection film 124.
The picture element electrodes 102 and the sub-patterns 132 partially overlap each other with the gate insulating film 110 and the protection film 124 therebetween, whereby sub-capacitances Cs are formed between the picture elements 102 and the gate bus lines 106.
Because the sub-patterns 132 also function as the light shield films, a pattern of the black matrix 134 to be formed on an opposed substrate is a region including the thin film transistor 104 above the picture element electrode 102, and a region between the gate bus line 106 and the picture element electrode 102.
In the thin film transistor matrix device of the Cs-on-Gate structure of FIG. 44A, the picture element electrode 102 is enclosed on only three sides thereof. A black matrix is necessary on the remaining one side, which results in lower aperture ratios.
As a countermeasure to this, a Cs-on-Gate structure in which the sub-patterns 132 are formed so as to enclose the picture element electrode 102 has been proposed. Such a Cs-on-Gate structure is shown in FIGS. 45A and 45B. FIG. 45A shows the pattern layout, and FIG. 45B shows the sectional view along the line C-C'.
In this thin film transistor matrix device, the sub-patterns 132 are extended further over the picture element electrode 102 in a ring-shaped pattern which encloses the picture element 102. This permits a pattern of the black matrix 134 which is to be formed on an opposed substrate to be able to shield only the thin film transistor 104, which results in very small alignment margins.
In the pattern of the thin film transistor matrix device as shown in FIGS. 45A and 45B, the gate bus lines neighbor each other over a long distance, which makes fabrication with high precision difficult, with a result of low fabrication yields. This is a problem.
On the other hand, as concerns the parasitic capacitance, in addition to the parasitic capacitances between the picture element electrodes and the gate bus lines, parasitic capacitances between the picture element electrodes are a problem. With large parasitic capacitances between the picture element electrodes, when data is written in picture element electrodes of a line adjacent to a line in the picture element electrodes in which data has been written, a potential of the picture element electrodes of the former line is changed by capacitive coupling. This is also a problem.
Accordingly, even in a case that there is ample allowance for the pattern, it is impossible to neighbor the picture element electrodes by, e.g., less than 5 .mu.m, and the aperture ratio cannot exceed a certain degree.
As a structure in which sub-capacitances are provided for large apparent capacitances, in addition to the above-described Cs-on-Gate structure, the so-called independent Cs structure has been proposed. That is, capacitance bus lines for the sub-capacitances Cs are provided independent of the gate bus lines, and the sub-capacitances Cs are provided on the capacitance bus lines.
FIG. 46 shows a conventional thin film transistor matrix device using the independent Cs structure.
Picture element electrodes 102 are arranged on a transparent insulating substrate in a matrix. A thin film transistor 104 is disposed on each picture element electrode 102. Each thin film transistor 104 includes a gate electrode 109, a drain electrode 120 and a source electrode 122. The gate electrodes 109 of the thin film transistors 104 are commonly connected to gate bus lines 106 provided widthwise as viewed in FIG. 46. The drain electrodes 120 of the thin film transistors 104 are commonly connected to drain bus lines 108 provided lengthwise as viewed in FIG. 46. The source electrodes 122 of the thin film transistors 104 are connected to the picture element electrodes 102 through contact holes 126.
To form a sub-capacitance Cs, an intermediate electrode 128 is provided at the center of each thin film transistor 102. The intermediate electrode 128 is connected to the picture element electrode 102 through a contact hole 130. A capacitance bus line 140 is provided below the intermediate electrode 128 widthwise as viewed in FIG. 46. A sub-capacitance Cs is formed between the intermediate electrode 128 and the capacitance bus line 140.
To shield light at the gaps between the picture element electrodes 102 of the thin film transistor matrix device, and the gate bus lines 106 and the drain bus lines 108 thereof, a light shield film 150 which is called a black matrix is formed on a substrate opposed to the TFT substrate.
In the independent Cs thin film transistor matrix device, however, for shielding the gaps by the black matrix, it is necessary to consider a margin corresponding to adhesion precision as shown in FIG. 46 in consideration of an adhesion error between the TFT substrate and the opposed substrate. This has made it difficult for the aperture ratio to exceed a certain ratio.
For aperture ratio improvement, it is proposed that light is shielded at the gaps without the use of the black matrix on the opposed substrate but by the use of the gate bus lines on the TFT substrate, the capacitance bus lines, etc. In a case that the light shield is effected by the pattern of the substrate of the thin film transistor matrix, higher alignment precision can be secured in comparison with the adhesion precision, which results in higher aperture ratios.
FIGS. 47A and 47B show one of the conventional thin film transistor matrix device in which the gate bus lines are used to shield light at the gaps. FIG. 47A shows its pattern layout, and FIG. 47B shows the sectional view along the line I-I'.
In the thin film transistor matrix device shown in FIGS. 47A and 47B, the gate bus lines 106 have a large width to thereby shield light at the gaps between the picture element electrodes 102 and the gate bus lines 106. The pattern on the TFT substrate, such as the gate bus lines 106, the capacitance bus lines 140, etc., are used to shield light at the gaps, whereby it is not necessary to consider a large alignment margin. High aperture ratios are available.
However, when the gate bus lines 106 are used to shield light at the gaps as shown in FIG. 47B, new capacitances Cgs are generated between the picture element electrodes 102 and the gate bus lines 106, and a direct current voltage change .DELTA.V of the picture element electrodes 102, i.e., a field through voltage .DELTA.V is given by the above-described formula (1) or (2). As seen from these formulas, as capacitances Cgs increase, field through voltages .DELTA.V increase, and a difference in the effective picture element voltage between the white display and the black display becomes large. This results in poor display quality.
There is also a problem that in shielding light at the gaps between the gate bus lines and the picture element electrodes by using the gate bus lines, deformation takes place in an orientation of the liquid crystal near the gate bus lines, and the deformation causes light leakage.
One example of the conventional thin film transistor matrix device in which light shielding at the gaps is conducted by the gate bus lines is shown in FIGS. 48 and 49. FIG. 48 shows the pattern layout, and FIG. 49 shows the sectional view along the line J-J'.
In the thin film transistor matrix device, as shown in FIG. 48, picture element electrodes 102 overlap gate bus lines 106 to shield light at the gap between the picture element electrodes 102. At the light shield parts, as shown in FIG. 49, deformation takes place in an orientation of the liquid crystal 142 between the picture element electrodes 102 and a common electrode 144. That is, a widthwise electric field is applied between the picture element electrodes and the common electrode 144 corresponding to a potential difference therebetween to orient the liquid crystal 142. In a case that an orientation of the widthwise electric field is opposite to that of the liquid crystal, as shown in FIG. 49, a reverse boundary 143 where a reversal of an orientation takes place in the liquid crystal 142 near an end of the picture element electrode 102. Light leaks at the reverse boundary. This a problem.
As described above, the conventional thin film transistor matrix devices must have high aperture ratios for light display and larger crystal capacities for higher display quality, but these criterion have not been sufficiently met.
The conventional thin film transistor matrix devices have patterns in which the gate bus lines neighbor each other over a rather long distance. This makes fabrication with good precision difficult, which results in low fabrication yields. This is a problem.
The conventional thin film transistor matrix device also has the problem that when data is written in adjacent picture element electrodes, a potential of the picture element electrodes is adversely changed due to capacitive coupling.
There is also a problem that due to a transverse electric field between the picture element electrodes and the gate bus lines, a boundary where an orientation is reversed appears in the liquid crystal, and light leaks at the boundary.